It is a common occurrence for defects to occur in parts of computer memory chips with embedded memories which result in non-functional parts of the memories. Conventionally, redundancy schemes are used to "repair" such defects on stand-alone memories while embedded memories without redundancy schemes are discarded.
Chips with embedded memories contain numerous cells, each cell having the capability of storing a high or a low voltage representing a "1" bit or a "0" bit respectively. The cells are interconnected in a grid with each row of cells commonly referred to as a word line, a set of word lines being a memory array. Each array has a unique multiplexed address which is controlled by an address generator. This structure of a chip with embedded memory is well known in the art and will not be further discussed here.
When a defective memory array is found during manufacturing tests, the conventional redundancy scheme attempts to replace sections of the damaged array with a redundant bit or word line using fuses. The fuses connecting the defective array portion to the functioning portions of the chip are broken while the fuses which would connect the redundant bit or word line are activated. In this way, defective parts of the chip are replaced and repaired.
A problem with the conventional redundancy scheme is that fuses require additional area on the chip. This can be a heavy penalty for conventional chips which are already very dense. In addition, fuses require additional manufacturing processes which increases the process complexity and manufacturing cost.
Another problem is its limited utility to defects found during manufacturing tests. If defects are introduced into memory during use, they cannot be addressed. The computer may suffer a shut-down without advance warning which would cost a user valuable time. This is a particular problem for computers running critical applications.
Therefore, there exists a need for a circuit for addressing memory defects which minimizes additional area on the chip and has utility subsequent to manufacturing testing. The present invention addresses such a need.